The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device in which the processing conditions of a non-cell region is improved to decrease a defect generating ratio at a cell array region, which ultimately increases the manufacturing yield.
Generally, in the manufacturing process of a semiconductor device, a number of steps are required to process a non-cell region to obtain a necessary cell array region that is needed for the highly integrated circuit chips. An alignment mark is an example of the non-cell region. The alignment mark is needed for a correct exposure of light onto a corresponding position of a circuit during numerous implementations of a photolithographic method that are required in the manufacture of the semiconductor device. The alignment mark is separately formed on a region such as a scribe line or an edge device that will be discarded after final production.
The role of the alignment mark will now be described in more detail. Conventionally, a semiconductor device is manufactured by repeating a process of depositing various materials and then patterning the same a number of times. A desired shape of a material layers is obtained by using the structure of a preceding layer. In other words, the preceding material layer and a photomask must be correctly aligned for the light exposure to obtain an accurate photoresist pattern during a number of accompanying photolithography processes.
However, as the deposition of various materials proceeds, the crookedness of the material layer gradually disappears and the circuit pattern on the cell array region becomes more complicated. Therefore, the correct alignment of the photomask for the subsequent layers over the underlying material layer becomes difficult. To solve this problem, a number of alignment marks are formed in a certain region, for example, on a scribe line, with respect to the material layers obtained at each step of the manufacturing process. The alignment marks are not integral parts of the device, but they are formed as a circuit of the non-cell region to assist the manufacturing process. Methods for manufacturing such alignment marks are disclosed by U.S. Pat. Nos. 5,369,050 (issued to Kawai), 5,663,099 (issued to Okave et al.) and 5,786,267 (issued to Karguchi et al.).
A lot ID illustrates another example of a non-cell region. The lot ID is formed in an appropriate region on a wafer by labeling a number or a symbol by means of a laser after inspecting the wafer and prior to processing the wafer for device manufacturing. The lot ID generally includes lot designating symbols and wafer designating symbols for differentiating each wafer. One lot includes one bundle of wafers to be processed by the manufacturing process. The lot ID, which is formed for the purpose of designation, is also used as an alignment mark as needed. However, the lot ID commonly becomes covered by various materials during the progression of the device manufacturing process.
Edge devices not having proper sizes of unit devices and which remain at the edge portions of the wafer, offer a third example of the non-cell region. The formation of the edge devices are due to the shape of the wafers. In other words, because the shape of the wafers is not square but is circular, a number of edge devices are formed along the edge portion of the wafers. Semiconductor devices are not formed on the edge devices but various layers of materials are formed on the edge region during the manufacturing process. Generally, alignment marks are formed on these edge devices.
In the non-cell region described above, the applied material formed on the cell array region during each step of the manufacturing process is also simultaneously formed. However, unlike in the cell array region, independent conductive patterns which are not earthen to the underlying silicone substrate, i.e., which are not connected to ground, are formed at the non-cell regions. As a result, the independent conductive patterns may be exposed during a subsequent dry etching using ion-assisted plasma. At this time, the generated ions and plasma may be electrically charged, and when a critical point has been reached by the movement of the etching plasma, the exposed independent patterns may instantaneously discharge, causing an arcing phenomenon. Once the arcing is generated, the region where the arcing has originated may melt or materials around the arcing generated portion may randomly tear off, potentially causing a 0% yield for the wafer. The arcing may also damage the existing alignment marks, resulting in a misalignment of the photomask with the cell array region during the subsequent photolithography process, also resulting in a decreased yield.
The arcing phenomenon will be explained in more detail with reference to the alignment mark. FIG. 1 is a cross-sectional view showing the structure of an alignment mark AM manufactured by a conventional method. A gate electrode material layer 12 including a polysilicone layer 12a and tungsten silicide (WSi) layer 12b, is formed on a silicone substrate 10. A first oxide layer 13 and a first insulation layer 14 are formed on the gate electrode material layer 12. The first oxide layer 13 is a high temperature thermal oxide layer, and the first insulation layer 14 is preferably an undoped silicate glass (USG) layer. A bit line material layer 15 is formed on the first insulation layer 14. The bit line material layer 15 includes a polysilicone layer 15a and a tungsten silicide layer 15b. A second insulation layer 16, i.e. a borophosphosilicate glass (BPSG) insulation layer, and a second oxide layer 17, which is another high temperature thermal oxide layer, are subsequently formed on the bit line material layer.
During the formation of the alignment mark (AM) by an integration of the various materials mentioned above, a cell array region of the device is formed as follows. A gate electrode is formed on the substrate and is then electrically insulated. Then, a bit line, which is connected to an impurity doped region, i.e. a source/drain region, is formed and is electrically insulated by depositing an insulating material on the substrate. Thereafter, a portion of the insulating material is removed to form a contact hole that exposes the impurity doped region, i.e. the source/drain region on the substrate. A storage node is then formed on the insulating material so that the source/drain region and the storage node are connected through the contact hole.
The structure illustrated in FIG. 1 is obtained at the step of forming a photoresist pattern 18 on the second oxide layer 17. The photoresist is formed by depositing a photoresist and then opening a portion to be etched for the formation of the contact hole. After this step, the portion opened by the photoresist pattern 18 is etched and removed down to the upper portion of the substrate to form the contact hole. At the same time, an etching is simultaneously implemented at the alignment mark region for the formation of an alignment mark that will be used for the subsequent photolithographic process. However, unlike in the cell array region, the gate electrode material layer 12 and the bit line material layer 15 are not earthen to the substrate, i.e., they are not connected to ground, and are independently formed as conductive patterns at the non-cell region. Accordingly, when an ion-assisted plasma dry etching is implemented and these independent conductive patterns are exposed to the plasma, arcing might be generated.
FIG. 2 is a cross-sectional view for showing the structure surrounding the alignment mark of FIG. 1 when an arcing is generated by a reactive ion etching process. The reference numeral 11 designates an etched portion around the alignment mark. The portion where the arcing is generated is melted away as shown by an arcing generating portion 19. Otherwise, the arcing generated portion tears off and the yield of the device becomes inevitably lowered.
FIG. 3 is a cross-sectional view for showing the structure around the alignment mark of FIG. 1 when a contact hole is not completely opened by the reactive ion etching process due to the generation of the arcing. This is also one factor which may contribute to the lowering of the yield. When the arcing is generated after the completion of etching and at the initial point of overetching, it is assumed that the yield of the wafer is lowered through the generation of the phenomenon illustrated in FIG. 2. When the arcing is generated during the implementation of an etching process, it is assumed that an etched portion 11 is not opened as illustrated in FIG. 3. At this time, the contact hole is only partially established on the cell array region, which can drop the yield of the wafer to 0%. This defect is caused by an insufficient etching of the region where the contact hole is to be formed, resulting from the lowering of an etching rate caused by the generation of heat at the arcing region.
The frequency and degree of the arcing depend on the material of the exposed conductive layer. According to repeated experiments by the present inventors, the most serious arcing is generated when a bit line formed by polysilicone/tungsten silicide is exposed to an ion-assisted plasma. Somewhat lighter arcing has been observed when a pad electrode is formed by polysilicone and the pad electrode is followed by a gate electrode formed by polysilicone/tungsten silicide. Furthermore, as the etching power for the ion-assisted plasma etching increases, the possibility of the arcing generation also increases.
Among the non-cell regions, a lot ID is formed by labeling a certain symbol by means of the laser on an appropriated region after inspecting a wafer and prior to implementing the device manufacturing process. During the manufacturing process, the lot ID becomes covered with various materials. These materials are usually used as an alignment mark or may be removed during the following process of forming subsequent layers.
After forming a bit line material layer, a BPSG insulation layer, a high temperature thermal oxide layer, and a photoresist pattern are formed on the lot ID. The high temperature thermal oxide layer, the BPSG insulation layer, and the bit line material layer formed on the lot ID are sometimes etched in this order during the step of forming a contact hole by using an ion-assisted plasma etching in order to expose the lot ID. At this time, the bit line material layer formed on the lot ID is an independent conductive pattern that is not earthen to the substrate, similar to an alignment mark, and thus can be a factor leading to the generation of an arc.
FIG. 4 is illustrated for showing the positions of a lot ID and an edge device on a wafer. As shown in FIG. 4, an edge device 4 and a lot ID 5 are formed at appropriate positions on a wafer 1.
Another factor that can generate arcing is the edge device region of the wafer. FIG. 5 is a cross-sectional view of an edge device region of a wafer manufactured by another conventional method. As compared to the device of FIG. 1, the structure shown in FIG. 5 is simplified, and the oxide layer is omitted.
First, the structure will be explained in brief. A gate electrode material layer 22, a first insulation layer 23, a bit line material layer 25, a second insulation layer 27, and a photoresist pattern 28 are sequentially formed on a silicone substrate 20. Thereafter, an ion-assisted plasma etching is implemented to open a contact hole on the cell array region. Because the wafer has a circular shape, it is difficult to form a device on its edge portion and after the completion of device fabrication in the cell array region, the edges are discarded. Accordingly, the edge region may be used as the alignment mark or may merely remain as an integrated structure of various materials. The position of an edge device 4 is designated in FIG. 4. When the edge device is used as an alignment mark, further problems may exist in addition to the generation of arcing.
During the device manufacturing, multiple photolithographic processes are used. In each photolithographic process, a photoresist is coated on a wafer to form a photoresist layer. The photoresist layer, which mainly includes organic material, is a flowing material. Therefore, the photoresist on the wafer flows to a side portion 20a to form an undesirable side photoresist layer. The distance between the side portion 20a of the wafer and a holding apparatus of the wafer is generally about 0.25-0.3 mm. However, the photoresist layer formed on the side portion 20a is thicker than the distance between these two and as a result, dried photoresist, which separates into particles, floats within an apparatus and may cause defects. In order to solve this problem, the edge portion of the wafer is separately exposed and the side portion of the wafer is rinsed using a solvent such as thinner. However, during the exposure and rinsing used to remove the side photoresist layer, an edge portion of the photoresist formed on the wafer also is inevitably exposed and removed.
For example, the edge portion of the photoresist pattern 28 that will be used for the formation of a contact hole is also partially removed by the side rinse process of removing the side photoresist layer as shown in FIG. 5. After the ion-assisted plasma etching for the formation of the contact hole, the portion of the layer under the photoresist pattern 28 remains while the portion of the layer not covered by the photoresist pattern 28 is removed. In other words, the portion of the layer outside of a dashed line 21 is removed for the conventional edge portion of the wafer as shown in FIG. 5. At this time, if an independent conductive pattern such as the bit line material layer 25 or the gate electrode material layer 22 is extended to the outer portion from the dashed line 21, the independent pattern becomes exposed to the ion-assisted plasma during the etching. In this case, the arcing may be generated during the etching or at the overetching point.
Thus, the prevention of the generation of arcing at the non-cell region caused by independent pattern which is not earthen, i.e., which is not connected to ground, during the manufacturing process of the device on the cell array region remains a very important problem to be resolved.
Accordingly, it is an object in the present invention to provide a method for manufacturing a semiconductor device of which manufacturing process for the non-cell regions is improved to decrease the generation of arcing at the same region, which will increase the yield of semiconductor devices.
To accomplish the object, a method is provided for manufacturing a semiconductor device. In this method, a conductive layer is formed over a cell array region in which high-integrated devices are formed and over a non-cell region that functions to assist a proper formation of the cell array region. An etching mask pattern is formed over the conductive layer. Then a conductive pattern is formed over the cell array region and a portion of the conductive layer formed over the non-cell region is removed, by etching the conductive layer using the etching mask pattern as a mask. Next, an ion-assisted plasma etching is implemented to form a pattern over the cell array region.
The non-cell region may include one of: an alignment mark used for properly aligning a mask and the cell array region during a photolithographic process, a lot ID for recognition of a wafer, which also functions as the alignment mark, and a region including the alignment mark and the lot ID. The conductive pattern may comprise polysilicone, tungsten silicide (WSi), or a composite layer containing both polysilicone and tungsten silicide. The conductive pattern is preferably selected from the group consisting of a bit line, a pad electrode, and a gate electrode. The etching mask pattern is preferably a photoresist pattern, most preferably a positive-type photoresist pattern.
The method may further comprise exposing a substrate on which a field isolation region is formed, the exposing being implemented by etching an oxide layer and an insulation layer formed over the non-cell region.
The object of the present invention also can be accomplished by the following method for manufacturing a semiconductor device. A plurality of highly-integrated devices are formed in a cell array region and a non-earthen conductive pattern is formed over a non-cell region of a substrate. An etching mask pattern is then formed that exposes a predetermined region over the cell array region and covers the non-cell region, and an ion-assisted plasma etching is implemented to etch the exposed region by the etching mask pattern.
The non-cell region preferably includes either an edge device formed on an edge region of a wafer, a lot ID for recognition of each wafer, or a region including the edge device and the lot ID. The conductive pattern preferably comprises polysilicone, tungsten silicide (WSi) or a composite layer containing both polysilicone and tungsten silicide. The conductive pattern is preferably selected from the group consisting of a bit line, a pad electrode, and a gate electrode. The ion-assisted plasma etching is preferably to implemented by reactive ion etching (RIE), magnetic enhanced reactive ion etching (MERIE), or thermo coupled plasma etching (TCPE). The output power during implementation of the ion-assisted plasma etching is preferably higher than 500W, most preferably in a range of about 1500-1700W.
The ion-assisted plasma etching is preferably implemented for the formation of a contact hole including a buried contact (BC) hole, a metal contact (MC) hole, and a direct contact (DC) hole. In this method, the etching mask pattern is preferably a photoresist pattern. The photoresist pattern of the edge device is preferably formed by forming a photoresist layer over the substrate and removing the photoresist layer formed over an edge portion, including a side portion of the substrate, by edge exposure and side rinse. A first distance from an end of the substrate to the photoresist pattern is shorter than a second distance from the end of the substrate to the conductive pattern.
A method for manufacturing a semiconductor device is also provided that includes the steps of forming a conductive layer over a cell array region, in which high-integrated devices are formed, and over a non-cell region, which functions to assist a proper formation of the cell array region; forming a photoresist pattern over the conductive layer; etching the conductive layer using the photoresist pattern as a mask to form a conductive pattern over the cell array region and to remove the conductive layer formed over the non-cell region; and implementing an ion-assisted plasma etching. In this method, the non-cell region includes an alignment mark for properly aligning a mask and the cell array region during a photolithographic process, or a lot ID for recognition of a wafer that functions as the alignment mark, the conductive pattern is selected from the group consisting of a bit line, a pad electrode, and a gate electrode, and the ion-assisted plasma etching is reactive ion etching (RIE) or magnetic enhanced reactive ion etching (MERIE).
A method for manufacturing a semiconductor device is also provided that includes forming a photoresist pattern to expose a predetermined region over a cell array region, in which high integrated devices are formed, and to cover a non-earthen conductive pattern formed over a non-cell region to assist a proper formation of the cell array region; and implementing an ion-assisted plasma etching using the photoresist pattern as a mask, to etching an exposed region. In this method, the non-cell region includes an edge device formed over an edge region of a wafer or a lot ID for recognition of each wafer, the conductive pattern is selected from the group consisting of a bit line, a pad electrode, and a gate electrode, and the ion-assisted plasma etching is reactive ion etching (RIE) or magnetic enhanced reactive ion etching (MERIE).
In the present invention, the generation of arcing phenomenon can be prevented by eliminating the independent conductive pattern, which is a factor of generating arcing during the ion-assisted plasma etching from the exposure of the plasma. The prevention is performed by removing or covering the independent conductive pattern before implementing the ion-assisted plasma etching.